Modeling of Electrical Overstress in Integrated Circuits

About this book

Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. Modeling of Electrical Overstress in Integrated Circuits presents a comprehensive analysis of EOS/ESD-related failures in I/O protection devices in integrated circuits.
The design of I/O protection circuits has been done in a hit-or-miss way due to the lack of systematic analysis tools and concrete design guidelines. In general, the development of on-chip protection structures is a lengthy expensive iterative process that involves tester design, fabrication, testing and redesign. When the technology is changed, the same process has to be repeated almost entirely. This can be attributed to the lack of efficient CAD tools capable of simulating the device behavior up to the onset of failure which is a 3-D electrothermal problem. For these reasons, it is important to develop and use an adequate measure of the EOS robustness of integrated circuits in order to address the on-chip EOS protection issue. Fundamental understanding of the physical phenomena leading to device failures under ESD/EOS events is needed for the development of device models and CAD tools that can efficiently describe the device behavior up to the onset of thermal failure.
Modeling of Electrical Overstress in Integrated Circuits is for VLSI designers and reliability engineers, particularly those who are working on the development of EOS/ESD analysis tools. CAD engineers working on development of circuit level and device level electrothermal simulators will also benefit from the material covered. This book will also be of interest to researchers and first and second year graduate students working in semiconductor devices and IC reliability fields.

Table of contents - (9 chapters)

About the authors

Carlos H. Díaz
Integrated Circuits Business Division, R&D Center, Hewlett-Packard Company, Palo Alto, USA
Dr. Díaz is a distinguished figure in the field of semiconductor technology, with a career spanning several decades and significant contributions to both industry and academia.
Dr. Díaz has published over 100 journal and conference papers and holds more than 225 U.S. patents. He has served on the IEEE International Electron Devices Meeting (IEDM) Technical and Executive Committees and participated in technical program committees for conferences such as IEEE VLSI, SSDM, SISPAD, IRPS, and EOS/ESD.
Dr. Díaz was elected an IEEE Fellow in 2008 for his contributions to deep-submicron foundry technology. In 2011, he co-received the Annual Innovation Breakthrough Award from Taiwan's Ministry of Economic Affairs for TSMC’s 28nm logic technology.
Dr. Carlos H. Díaz's extensive experience and contributions have significantly advanced the field of semiconductor technology, influencing both current practices and future directions in the industry

Sung-Mo Kang
Coordinated Science Laboratory, University of Illinois, Urbana, USA

Charvaka Duvvury

Semiconductor Process and Design Center, Texas Instruments Incorporated, Dallas, USA